1. Field of Invention
The present invention relates generally to the field of digital filters in mixed-signal communication channels.
2. Description of Related Art
Signal processing in digital communications is concerned with optimizing performance given the constraints of power, noise, bandwidth limitations, area, memory, sampling limitations and numerous other requirements depending on the architecture employed.
Data communication is moving away from parallel busses and towards serial transmission and serial protocols. System designers are under pressure to reliably send data over low bandwidth channels at rates for which they may not have been optimally designed for, and to pack more communication channels into smaller and smaller spaces. This results in increasingly poorer receive signal levels and higher levels of crosstalk, among other problems.
To handle the low bandwidth channels, many receiver designs employ some sort of equalization to boost high frequency signals that are attenuated as the signal passes through the channel. This might be realized using a linear high pass filter, that boosts the high frequency signal was well any associated noise, and thus the signal-to-noise ratio (SNR) remains poor.
As many communication channels effectively act as low-pass filters, decision feedback equalization/equalizers (DFE) are used to help remove noise and distortion of digital signals, such as intersymbol interference (ISI) caused by attenuation of high frequencies.
Some of the problems associated with digital signal processing as addressed by DFE are outlined in U.S. Pat. No. 6,437,932 to Prater et al., commonly assigned to the present assignee, and incorporated herein in its entirety.
To combat such poor SNR and recover data in systems with low SNR, designers have developed decision feedback equalization.
For example, turning attention to FIG. 1, there is shown a decision feedback equalization (DFE) schematic of the kind used in high-speed serial communications. Transmit data TXDATA is sent through the channel having transfer function H(s), and may be distorted by the channel. A capture flip-flop 1, such as a D latch, has an output Q that follows changes in the data input D as long as control input clock CLK is enabled, and holds the binary information present at the data input when the clock CLK is disabled, until such time the clock CLK is enabled again. Capture flip-flop 1 samples the output of summing circuit 3, which has inputs for the data TXDATA coming out of the communication channel, having an impulse transfer function H(s), as well as the negative feedback signal output by summer 2. The capture flip-flop 1 samples the data at the rising edge of clock CLK, and decides whether the incoming data is a binary 1 or a 0 at that instant. Assuming the capture flip-flop 1 makes the correct decision (subject to the usual rules for sampling and the like), the correct data shows up as a bit stream at RXDATA.
To achieve feedback in FIG. 1, the bit stream is passed through a discrete-time FIR (Finite Impulse Response) digital filter that approximates the impulse response of the channel H(s), that is:
      H    ⁡          (      s      )        ≅            ∑              n        =        0                    N        -        1              ⁢          h      n      
The result, after passing through n-order coefficients for the FIR comprising Tap Weight DAC (digital-to-analog converters) and being summed, is subtracted at summing circuit 3 from the incoming signal.
The negative feedback at summing circuit 3 has the effect of boosting the high-frequency content of the incoming signal, however, due to the digital, quantized nature of the feedback, the unwanted noise at the input is not boosted.
The DFE of FIG. 1 implemented by discrete-time FIR filters has a number of difficulties that the present invention seeks to overcome. For the DFE of FIG. 1 to work properly, the feedback from the output of each D flip-flop/latch as shown in FIG. 1, fed through the tap weights DAC, and the summing node 3, must occur in less than one bit time. This condition places strict requirements on the flip-flop clock-to-Q time, the propagation time through the tap weight DACs, and the summing node 3. To meet this condition in the FIG. 1 DFE requires high bandwidth within the circuit and the circuit consumes much power. While the bandwidth requirements can be alleviated for all taps except the h0 term by using a multi-phase architecture, this requires duplication of circuitry and thus requires more power and chip area to implement.
Furthermore, for the DFE system of FIG. 1 to work, the capture flip-flop clock (CLK) has to be generated by a phase locked loop (PLL) that locks to rate of the incoming data TXDATA as it leaves the channel and is received at the input of the summer 3. The operation of the equalizer relies on this clock being properly locked to this incoming data TXDATA. Since the clock recovery PLL extracts timing information from the recovered data RXDATA, the operation of the clock recovery PLL depends to some extent on the correct operation of the equalizer. This interdependence can make the operation of the discrete-time DFE of FIG. 1 somewhat temperamental and sensitive to disturbance.
Factoring all of the above, it can be seen that what is needed is a superior method and apparatus for a DFE of the kind used in high-speed serial transmission of digital data.